1. Field of the Invention
The present invention relates to a multi processor system which is a computer system having a plurality of processors and to a FIFO circuit applicable to the multi processor system.
2. Description of the Related Art
Computers are always required to have high-speed operations and high performance. In order to implement the requirements, parallel processing of a plurality of instructions is adopted. There are, as typical methods of parallel processing, a method in which the number of instructions which can be processed in parallel by a single processor is increased and a method in which a plurality of processors are used so that the number of instructions which can be processed in parallel is increased.
The multi processor system having a plurality of processors has been implemented in a large scale computer system such as a super computer. The number of processors is increased to improve the performance of the multi processor system. Thus, a type of multi processor system in which the number of processors can be easily increased is in the mainstream.
An example of a conventional multi processor system is formed as shown in FIG. 1. Referring to FIG. 1, the multi processor system has processors 1-1, 1-2, . . . , 1-n, a bus 2 and a shared memory 3. The bus 2 is connected with the plurality of processors 1-1, 1-2, . . . , 1-n and the shared memory 3 which is shared by the processors 1-1, 1-2, . . . , 1-n.
Another example of a conventional multi processor system is formed as shown in FIG. 2. Referring to FIG. 2, the multi processor system has processors 4-1, 4-2, . . . , 4-n and a crossbar network 5. The processors 4-1, 4-2, . . . , 4-n are coupled to each other via crossbar switches in the crossbar network 5.
In the conventional multi processor system as shown in FIG. 1, when a request for delivery of data between two processors and a request for delivery of data between two other processors are issued, the data delivery operations in response to the requests are mediated so that one of the data delivery operations is awaited. Thus, the data can not be processed at a high speed.
In addition, as to data transmission, the data is transmitted via the bus 2 always. Thus, a bus transaction in which data is transmitted after a bus right is obtained is needed. From this viewpoint, also, the high speed data processing deteriorates.
In the conventional multi processor system as shown in FIG. 2, as far as processors do not conflict with each other on a crossbar switch used to connect to other processors, the wait for the data delivery operation does not occur. However, if processors conflict with each other on a crossbar switch, one of the data delivery operations is awaited in the same manner as in the case of the multi processor system shown in FIG. 1. This matter prevents data from being processed at a high speed.
In addition, since a large number of crossbar switches have to be provided in the crossbar network 5, the circuitry structure of the system is complex. The data must be transmitted via crossbar switches. From this viewpoint, also, the high speed data processing is prevented.
Accordingly, a general object of the present invention is to provide a novel and useful multi processor system in which the disadvantages of the aforementioned prior art are eliminated.
A specific object of the present invention is to provide a multi processor system by which data can be processed at a high speed.
Another object of the present invention is to provide a multi processor system having a simplified circuitry structure.
The above objects of the present invention are achieved by a multi processor system comprising: a first processor, having a data input terminal and a data output terminal, which first processor is programmed so as to decide destinations to which data items successively input from an input terminal thereto should be delivered and deliver the input data times to the decided destinations; and a plurality of second processors, each of which has a data input terminal and a data output terminal and is programmed so as to execute a predetermined process for data delivered from the first processor.
According to the multi processor system of the present invention, the plurality of second processors can execute processes in parallel. Since input data items are delivered from the first processor to the plurality of second processors, it is not necessary for the multi processor system to provide a bus shared by the plurality of second processors as shown in FIG. 1 or provide a crossbar network as shown in FIG. 2.
As a result, there is no case in which each of the second processors is waiting for the data transmission operation. In addition, a procedure for obtaining the bus right is not needed.
A further object of the present invention is to provide a FIFO circuit in which data items used by a master can be reused by another master without spoiling a function, of a FIFO, that data items input thereto are output in the inputting order.
The above object of the present invention is achieved by providing a FIFO circuit comprising: a memory portion; a write pointer assigned to a first master; and a plurality of read pointers each of which is assigned to one of a plurality of second masters.
In the FIFO circuit according to the present invention, write and read operations with respect to the memory portion may be executed under a condition in which an address specified by the first master using the write pointer does not exceed an address specified by one of the plurality of second masters using a corresponding one of the plurality of read pointers which one executes a read operation for each of data items in the memory portion last. In this case, the data items can be used by the plurality of second masters. Thus, the data items in the memory portion can be reused without spoiling a function, as the FIFO, that data items input thereto are output in the inputting order.